Technique Produces Nano Shapes on Chips Using High-Precision Tip Tool
The Nanomanufacturing Systems for Mobile Computing and Mobile Energy Technologies (NASCENT) Engineering Research Center, in collaboration with industry partner Zyvex Labs, established a process for creating extremely small, high-resolution patterns for semiconductors by using the novel technique of “tip-based fabrication.”
The work paves the way for allowing semiconductor chip designers to experiment with a highly customizable array of small-scale patterns. In a commercial application, these patterns would populate the templates for silicon wafers used in mass-producing integrated circuits. Successfully producing such circuits at a relatively large “wafer scale” could dramatically drive down costs (by reducing defects) while making possible significant leaps in device performance and functionality.
The collaboration could prove useful in the future for designing experiments that examine various shapes for use in the integrated circuits of planned devices.
Tip-based fabrication involves the use of a tiny probe to precisely assemble molecules of a material (such as silicon) at the nano scale—generally regarded to be between 1 and 100 nanometers. Tip-based fabrication itself won’t be used to produce advanced circuits on the scale of an entire wafer (which can measure several inches in diameter). It can, however, be used to create extremely high-resolution features for the purposes of design and testing.
NASCENT is a National Science Foundation-funded Nanosystems Engineering Research Center (NERC) that is headquartered at the University of Texas, Austin.