Advanced Electronics through Machine Learning
The Center for Advanced Electronics Through Machine Learning (CAEML) enables fast, accurate design and verification of microelectronic circuits and systems by creating machine-learning algorithms to derive models for electronic design automation.
Electronic design automation must advance in response to increasingly ambitious goals for low power, high performance, and a short design cycle time, as well as to increasing concerns about security. Existing machine-learning techniques fall short when applied to systems with many ports, which contain reliability hazards and have nonlinear responses and variability. There is an unmet need for models, methods, and tools that enable fast, accurate design and verification while protecting intellectual property. A behavioral approach to systems modeling will meet this need. CAEML develops new domain-specific machine-learning algorithms to produce models using limited training data. Designers’ knowledge is used to speed up learning and impose physical constraints on the models.
CAEML pioneers the application of emerging machine-learning techniques to microelectronics and microsystems modeling. CAEML collaborates with microelectronics industry partners, whose products include electronic design automation tools, integrated circuits, mobile systems, and hardware for cloud computing. Working closely with these industry partners ensures that CAEML provides models and tools that will facilitate communications between customers and suppliers while protecting the proprietary information of all parties. This will lead to more efficient and reliable production.
Back-end integrated circuit design
CAEML uses machine learning to set up customized physical design tools to achieve optimal results with minimal human interaction.
Computationally efficient simulation of circuit aging including stochastic effects
CAEML is developing a method for accurate and efficient simulation of circuit aging due to hot carrier injection and bias temperature instability. Computational efficiency is achieved by using a recurrent neural network to represent a library cell or IP block.
Enabling side-channel attacks on post-quantum protocols through machine learning
CAEML enables single-trace power, side-channel attacks on post-quantum key-exchange protocols using machine learning and quantifies the strength of timing obfuscation defenses against those attacks.
High-dimensional structural inference
In many applications, a time series of high-dimensional latent vector variables is observed indirectly from noisy measurements. CAEML’s research investigates deep Markov models, in which an inference network approximates a posterior probability for the time-dynamics of latent variables by running a multilayer perceptron neural network.
High-speed bus physical design analysis
CAEML is creating a dynamic machine-learning ecosystem to characterize electrical performance of each net in a given printed circuit board or package layout file with confidence bounds and to leverage pre-physical design simulation to collect training data. Stochastic collocation is used to account for manufacturing tolerance and nets will be ranked in descending order of signal integrity performance to determine any bottleneck in the system.
Machine learning to predict successful field programmable gate arrays (FPGA) compilation strategies
CAEML is producing FPGA compilation recipes that show a high success rate and fast compilation time.
Modular machine learning for behavioral modeling of microelectronic circuits and systems
CAEML combines the inherent modularity of modern machine-learning algorithms with the behavioral approach to system design and simulation, to develop mathematical tools for assessing the performance and minimal data requirements for learning a low-complexity representation of the system behavior, one component or subsystem at a time.
Power/performance/area (PPA) prediction
CAEML builds machine learning models and develops associated tools to predict PPA given a register-transfer level description of a circuit, eliminating the need to undertake the lengthy physical design process. To maximize the accuracy of PPA predictions while minimizing the data collection effort, CAEML also is developing a comprehensive data mining methodology.
Trusted platform design
CAEML uses machine-learning techniques to assess whether an “internet of things” system is under cyberattack via power or radio frequency side channels and develop hardware countermeasures to identify and nullify such attacks.
Notice: Please contact international@erc-assoc.org if you represent this Research Institution and have identified any required additions or modifications to the above information.